baru saja mikir, makin lama makin ketebak
kalo melihat data, kemungkinan SoC ARM sekelas Snapdragon 845
konfigurasinya seperti ini (jadi mirip A10X deh)
L1 cache Per core: 64 KiB instruction + 64 KiB data (estimated)
L2 cache 3 MiB (estimated)
L3 cache 4 MiB (estimated)
jumlah transistor sekitar 5 M lebih
kalau begitu mungkin A11 tinggal buka saja L1 cache ke 64 KiB (atau lebih)
dan tambah core (kalo perlu L3 cache diadakan)
teorinya gini kalo A11X-A12-A12X-A13 (lanjutannya juga pake big.LITTLE), gw copas aja daripada capek
tapi lumayan lama buat realisasinya
The ring big.LITTLE-logy had a lot of combos (it ran very very fast, if up to 3.0GHz with Parallel-JIT). The Ring should run at up to 3.0GHz, while the current technology and L3-cache runs at at between 1.6GHz and 2.8GHz. As result, the L3-cache latency was pretty low: if the core is lucky enough to find the data in its own cache slice, only one extra cycle is needed (on top of the normal L1-L2-L3 latency). Getting a cacheline of another slice can cost up to 4 cycles, with an average cost of 2 cycles. Still, according to SoC the average latency to the L3-cache is only 30-10% higher, and the power usage is lower. Peak memory bandwidth and capacity is quite a bit higher with 4 dies and 2 memory channels per die. However, there is no central last level cache that can perform low latency data coordination between the L2-caches of the different cores. The latency difference between accessing a local L3-cache chunk and one further away is negligible on average, allowing the L3-cache to be a central storage for fast data synchronization between the L2-caches. As result, the 8x8 MiB L3-caches acts like - relatively low latency - spill over caches for the 32 L2-caches on one chip.
nb: berarti range harga SoC max 50 USD, wkwkwk (kalo pake cache gede)